1. Field of the Invention
The present invention relates generally to split gate field effect transistor (FET) devices, as employed within semiconductor integrated circuit microelectronic fabrications. More particularly, the present invention relates to split gate field effect transistor (FET) devices with enhanced properties, as employed within semiconductor integrated circuit microelectronic fabrications.
2. Description of the Related Art
In addition to conventional semiconductor integrated circuit microelectronic fabrications having formed therein conventional field effect transistor (FET) devices and conventional bipolar junction transistor (BJT) devices whose transient operation provides for data storage and transduction capabilities within the conventional semiconductor integrated circuit microelectronic fabrications, there also exists within the art of semiconductor integrated circuit microelectronic fabrication non-volatile semiconductor integrated circuit microelectronic fabrications, and in particular non-volatile semiconductor integrated circuit microelectronic memory fabrications, such as but not limited to electrically erasable programable read only memory (EEPROM) non-volatile semiconductor integrated circuit microelectronic memory fabrications, whose data storage and transduction capabilities are not predicated upon transient operation.
Although non-volatile semiconductor integrated circuit microelectronic memory fabrications, such as but not limited to electrical erasable programmable read only memory (EEPROM) non-volatile semiconductor integrated circuit microelectronic memory fabrications, may be fabricated while employing any of several semiconductor integrated circuit microelectronic devices, a particularly common semiconductor integrated circuit microelectronic device employed within an electrically erasable programmable read only memory (EEPROM) non-volatile semiconductor integrated circuit microelectronic memory fabrication is a split gate field effect transistor (FET) device.
A split gate field effect transistor (FET) device is in part analogous in structure and operation with a conventional field effect transistor (FET) device insofar as a split gate field effect transistor (FET) device also comprises formed within a semiconductor substrate a channel region defined by a pair of source/drain regions also formed within the semiconductor substrate, wherein at least the channel region of the semiconductor substrate has formed thereupon a gate dielectric layer which separates a gate electrode from the channel region of the semiconductor substrate, but a split gate field effect transistor (FET) device is nonetheless distinguished from a conventional field effect transistor (FET) device by employing rather than a single gate electrode positioned upon the gate dielectric layer and completely covering the channel region of the semiconductor substrate: (1) a floating gate electrode positioned upon the gate dielectric layer and covering over only a portion of the channel region defined by the pair of source/drain regions (such portion of the channel region also referred to as a floating gate electrode channel region); and (2) a control gate electrode positioned over the gate dielectric layer and covering a remainder portion of the channel region while at least partially covering and overlapping the floating gate electrode while being separated from the floating gate electrode by an inter-gate electrode dielectric layer (such remainder portion of the channel region also referred to as a control gate electrode channel region).
In order to effect operation of a split gate field effect transistor (FET) device, particular sets of voltages are applied to the control gate electrode, the source/drain regions and the semiconductor substrate in order to induce, reduce or sense charge within the floating gate electrode (which is otherwise fully electrically isolated) and thus provide conditions under which the floating gate electrode within the split gate field effect transistor (FET) device may be programmed, erased and/or read.
While split gate field effect transistor (FET) devices are thus desirable within the art of semiconductor integrated circuit microelectronic fabrication for providing semiconductor integrated circuit microelectronic fabrications with non-volatile data storage characteristics, split gate field effect transistor (FET) devices are nonetheless not entirely without problems in the art of semiconductor integrated circuit microelectronic fabrication.
In that regard, it is often difficult to form within non-volatile semiconductor integrated circuit microelectronic fabrications split gate field effect transistor (FET) devices with enhanced properties, and in particular with enhanced registration properties, such as but not limited to enhanced control gate electrode to floating gate electrode registration properties, within the split gate field effect transistor (FET) devices.
It is thus towards the goal of providing for use within semiconductor integrated circuit microelectronic fabrications, and in particular within semiconductor integrated circuit microelectronic memory fabrications, methods for fabricating split gate field effect transistor (FET) devices with enhanced properties, and in particular with enhanced registration properties, that the present invention is directed.
Various non-volatile semiconductor integrated circuit microelectronic devices having enhanced properties, such as but not limited to enhanced registration properties and enhanced alignment properties, and methods for fabrication thereof, have been disclosed within the art of non-volatile semiconductor integrated circuit microelectronic fabrication.
For example, Sung et al., in U.S. Pat. No. 5,940,706, disclose a method for fabricating within a split gate field effect transistor (FET) device a channel region within the split gate field effect transistor (FET) device, wherein the channel region within the split gate field effect transistor (FET) device is fabricated with enhanced location definition of the channel region within the split gate field effect transistor (FET) device and enhanced lateral size definition of the channel region within the split gate field effect transistor (FET) device. To realize the foregoing objects, there is employed when fabricating the split gate field effect transistor (FET) device a single composite mask layer, a series of patterned features of which are employed for defining both: (1) a floating gate electrode location and lateral size within the split gate field effect transistor (FET) device; and (2) a drain region location and lateral size with respect to the floating gate electrode location and lateral size within the split gate field effect transistor (FET) device.
In addition, Hsieh et al., in U.S. Pat. No. 6,017,795, disclose a method for fabricating a split gate field effect transistor (FET) device, as well as the split gate field effect transistor (FET) device fabricated in accord with the method, wherein there is provided within the split gate field effect transistor (FET) device an enhanced coupling ratio between a floating gate electrode within the split gate field effect transistor (FET) device and a source region within the split gate field effect transistor (FET) device. To realize the foregoing object, the method for fabricating the split gate field effect transistor (FET) device, and the split gate field effect transistor (FET) device resulting from the method, employ a source region partially topographically protruding with a sharp edge from a surface of a semiconductor substrate, in conjunction with a gate dielectric layer and a floating gate electrode formed conformally registered upon the sharp edge of the source region partially topographically protruding from the surface of the semiconductor substrate.
Desirable within the art of non-volatile semiconductor integrated circuit microelectronic fabrication, and in particular within the art of non-volatile semiconductor integrated circuit microelectronic memory fabrication, are additional methods and materials which may be employed for forming split gate field effect transistor (FET) devices with enhanced properties, and in particular with enhanced registration properties.
It is towards the foregoing object that the present invention is directed.
A first object of the present invention is to provide a method for fabricating, for use within a semiconductor integrated circuit microelectronic fabrication, a split gate field effect transistor (FET) device.
A second object of the present invention is to provide a method in accord with the first object of the present invention, wherein the split gate field effect transistor (FET) device is fabricated with enhanced properties.
A third object of the present invention is to provide a method in accord with the first object of the present invention and the second object of the present invention, wherein the method is readily commercially implemented.
In accord with the objects of the present invention, there is provided by the present invention a method for fabricating a split gate field effect transistor (FET) device, and a split gate field effect transistor (FET) device resulting from the method. To practice the method of the present invention, there is first provided a semiconductor substrate. There is then formed upon the semiconductor substrate a gate dielectric layer. There is then formed upon the gate dielectric layer a blanket floating gate electrode material layer. There is then formed upon the blanket floating gate electrode material layer a patterned mask layer. There is then etched, while employing the patterned mask layer as an etch mask layer, the blanket floating gate electrode material layer to form a floating gate electrode. There is then etched laterally, at least partially, the patterned mask layer to completely expose an edge of the floating gate electrode. There is then formed covering the floating gate electrode an inter-gate electrode dielectric layer. There is then formed upon the inter-gate electrode dielectric layer a control gate at least partially covering the floating gate electrode and at least partially not covering the floating gate electrode. Finally, there is also formed into the semiconductor substrate a pair of source/drain regions which define a floating gate electrode channel with respect to the floating gate electrode and an adjoining control gate electrode channel with respect to the control gate electrode.
The method of the present invention contemplates a split gate field effect transistor (FET) device fabricated in accord with the method of the present invention.
The present invention provides a method for fabricating within a semiconductor integrated circuit microelectronic fabrication, and in particular within a non-volatile semiconductor integrated circuit microelectronic memory fabrication, a split gate field effect transistor (FET) device, wherein the split gate field effect transistor (FET) device is fabricated with enhanced properties, and in particular with enhanced registration properties. The present invention realizes the foregoing objects by laterally etching, subsequent to forming a floating gate electrode by etching of a blanket floating gate electrode material layer while employing a mask layer, the mask layer to completely expose an edge of the floating gate electrode, prior to forming covering the floating gate electrode a blanket inter-gate electrode dielectric layer in turn having formed thereupon a control gate electrode. By completely exposing the edge of the floating gate electrode in such a fashion, there results an enhanced registration of the control gate electrode with respect to the floating gate electrode, and in particular with respect to the floating gate electrode edge, and consequently there also results enhanced erasing properties within the split gate field effect transistor (FET) device fabricated in accord with the present invention.
The method of the present invention is readily commercially implemented. A split gate field effect transistor (FET) device fabricated in accord with the present invention employs process steps and materials as are generally known in the art of semiconductor integrated circuit microelectronic fabrication, including but not limited to non-volatile semiconductor integrated circuit microelectronic memory fabrication, but employed within the context of a novel ordering and sequencing of process steps to provide a split gate field effect transistor (FET) device in accord with the present invention. Since it is thus a novel ordering and sequencing of process steps which provides at least in part the present invention, rather than the existence of methods and materials which provides the present invention, the method of the present invention is readily commercially implemented.